1. Field of the Invention
The present invention relates to a D-FF circuit. In particular, the present invention relates to a D-FF circuit which is operated in accordance with a clock signal generated by a clock signal generating circuit.
2. Description of the Related Art
According to an earlier development, a D-flip-flop (hereinafter, referred to as xe2x80x9cD-FFxe2x80x9d) made from CMOS (Complementary MOS) comprises a flip-flop for a master part (hereinafter, referred to as xe2x80x9cmaster FFxe2x80x9d), a flip-flop for a slave part (hereinafter, referred to as xe2x80x9cslave FFxe2x80x9d) and a clock signal generating circuit. The clock signal generating circuit generates a clock signal to output the clock signal to the master FF and the slave FF. The master FF and the slave FF start or stop each operation at each timing in accordance with the outputted clock signal, respectively.
With reference to FIGS. 3A, 3B and 4, a D-FF circuit 100 according to an earlier development, will be explained.
FIG. 3A is a view showing a D-FF circuit 100 according to an earlier development. FIG. 3B is a view showing a clock signal generating circuit 200 of the D-FF circuit 100.
In FIG. 3A, the D-FF circuit 100 comprises a master FF having inverters 101 and 102, transfer gates G1 and G2 and a NAND gate 106, and a slave FF having transfer gates G3 and G4, a NAND gate 107 and inverters 103, 104 and 105. The master FF and the slave FF start or stop each operation in accordance with the clock signal outputted from the clock signal generating circuit 200, respectively.
The transfer gates G1, G2, G3 and G4 comprise P-channel transistors Tr5 to Tr8 and N-channel transistors Tr1 to Tr4, respectively. The clock signal outputted from the clock signal generating circuit 200 is inputted into each transistor Tr1 to Tr8. Each transfer gate G1, G2, G3 and G4 is in an xe2x80x9cONxe2x80x9d state or in an xe2x80x9cOFFxe2x80x9d state according to the clock signal inputted into each transistor Tr1 to Tr8. These transfer gates hold or transmit an input signal data.
As shown in FIG. 3B, the clock signal generating circuit 200 comprises three inverters 31, 32 and 33. The inverter 31 inverts an input clock signal CLK to output a first clock signal {overscore (CLK1)}. The inverter 32 inverts the first clock signal {overscore (CLK1)} to output a second clock signal CLK2. The inverter 33 inverts the second clock signal CLK2 to output a third clock signal {overscore (CLK2)}.
The second clock signal CLK2 and the third clock signal {overscore (CLK2)} are used as clock signals for stopping the operation of the master FF. The first clock signal {overscore (CLK1)} and the second clock signal CLK2 are used as clock signals for starting the operation of the slave FF.
The operation of the D-FF circuit 100 which is constructed as described above, will be explained with reference to the operation timing chart shown in FIG. 4. In FIG. 4, the solid lines show the operation of the D-FF circuit 100 in the rising of the input signal data. The alternate long and short dash lines show the operation of the D-FF circuit in the falling of the input signal data.
First, the operation of the D-FF circuit in the rising of the input signal data, will be explained with reference to the waveforms drawn by the solid lines shown in FIG. 4.
At the time t50, when the voltage of the input signal data rises from a xe2x80x9cLxe2x80x9d level to a xe2x80x9cHxe2x80x9d level, the inverter 101 inverts the input signal data to output a xe2x80x9cLxe2x80x9d level signal. At the same time, because the second clock signal CLK2 is in a xe2x80x9cLxe2x80x9d level and the third clock signal {overscore (CLK2)} is in a xe2x80x9cHxe2x80x9d level, the transfer gate G1 is in an xe2x80x9cONxe2x80x9d state. Therefore, the transfer gate G1 outputs the xe2x80x9cLxe2x80x9d level signal which is outputted from the inverter 101, to the inverter 102. The inverter 102 inverts the inputted xe2x80x9cLxe2x80x9d level signal to output a xe2x80x9cHxe2x80x9d level signal. At the time t51, the voltage of the signal falls from a xe2x80x9cHxe2x80x9d level to a xe2x80x9cLxe2x80x9d level at a node N2. At the time t52, the voltage of the signal rises from a xe2x80x9cLxe2x80x9d level to a xe2x80x9cHxe2x80x9d level at a node N3.
On the other hand, in the clock signal generating circuit 200, at the time t52, the voltage of the input clock signal CLK rises from a xe2x80x9cLxe2x80x9d level to a xe2x80x9cHxe2x80x9d level. An external set up time which is the period from the time that the input data is inputted to the time that the voltage of the input clock signal rises, is from the time t50 to the time t52.
The input clock signal CLK is inverted by the inverter 31. At the time t53, a xe2x80x9cLxe2x80x9d level first clock signal {overscore (CLK1)} is outputted. The first clock signal {overscore (CLK1)} is inverted by the inverter 32. At the time t55, a xe2x80x9cHxe2x80x9d level second clock signal CLK2 is outputted. Because the first clock signal {overscore (CLK1)} is in a xe2x80x9cLxe2x80x9d level and the second clock signal CLK2 is in a xe2x80x9cHxe2x80x9d level, the transfer gate G3 is in an xe2x80x9cONxe2x80x9d state and starts the operation of the slave FF.
When the operation of the slave FF is started at the time t55, a xe2x80x9cHxe2x80x9d level signal which passes through a node N3 at the time t52, passes through the transfer gate G3. At the time t57, the voltage of the signal rises from a xe2x80x9cLxe2x80x9d level to a xe2x80x9cHxe2x80x9d level at a node N5.
At the time t56, the second clock signal {overscore (CLK1)} passes through the inverter 33 of the clock signal generating circuit 200. The inverter 33 outputs a xe2x80x9cLxe2x80x9d level third clock signal {overscore (CLK2)}. Then, the transfer gate G1 is in an xe2x80x9cOFFxe2x80x9d state. The operation of the master FF is stopped and the master FF holds the input signal data.
Next, the operation of the D-FF circuit in the falling of the input signal data, will be explained with reference to the waveforms drawn by the alternate long and short dash lines.
At the time t50, when the voltage of the input signal data falls from a xe2x80x9cHxe2x80x9d level to a xe2x80x9cLxe2x80x9d level, the inverter 101 inverts the input signal data to output a xe2x80x9cHxe2x80x9d level signal. At the same time, because the second clock signal CLK2 is in a xe2x80x9cLxe2x80x9d level and the third clock signal {overscore (CLK2)} is in a xe2x80x9cHxe2x80x9d level, the transfer gate G1 is in an xe2x80x9cONxe2x80x9d state. Therefore, at the time t52, the voltage of the signal rises from a xe2x80x9cLxe2x80x9d level to a xe2x80x9cHxe2x80x9d level at the node N2. The signal which passes through the node N2, is inverted by inverter 102. At the time t54, the voltage of the signal falls from a xe2x80x9cHxe2x80x9d level to a xe2x80x9cLxe2x80x9d level at the node N3.
On the other hand, in the clock signal generating circuit 200, at the time t52, the voltage of the input clock signal rises from a xe2x80x9cLxe2x80x9d level to a xe2x80x9cHxe2x80x9d level. The input clock signal CLK is inverted by the inverter 31. At the time t53, a xe2x80x9cLxe2x80x9d level first clock signal {overscore (CLK1)} is outputted. The first clock signal {overscore (CLK1)} is inverted by the inverter 32. At the time t55, a xe2x80x9cHxe2x80x9d level second clock signal CLK2 is outputted. Because the first clock signal {overscore (CLK1)} is in a xe2x80x9cLxe2x80x9d level and the second clock signal CLK2 is in a xe2x80x9cHxe2x80x9d level, the transfer gate G1 is in an xe2x80x9cOFFxe2x80x9d state. The operation of the master FF is stopped and the master FF holds the input signal data.
At the time t61, the voltage of a reset signal RB falls from a xe2x80x9cHxe2x80x9d level to a xe2x80x9cLxe2x80x9d level. Then, at the time t62, the voltage of the signal rises from a xe2x80x9cLxe2x80x9d level to a xe2x80x9cHxe2x80x9d level at the node N2. At the time t63, the voltage of an output signal OUT rises from a xe2x80x9cLxe2x80x9d level to a xe2x80x9cHxe2x80x9d level. An external reset time tR (the period from the time that the reset signal is inputted to the time that the output signal {overscore (OUT)} is reset) is from the time t61 to the time t63.
However, in the D-FF circuit according to an earlier development, which is shown in FIG. 3, when the voltage of the input signal data falls, there are many cases that a current supply capacity of the P-channel transistor Tr5 of the transfer gate G1 is not sufficient. Therefore, the rise-time that the voltage of the signal rises at the node N2, is slow (long). In contrast to the P-channel transistor Tr5, there are many cases that a current supply capacity of the N-channel transistor Tr1 is sufficient. Therefore, the fall-time that the voltage of the signal falls at the node N2, is fast (short). On the other hand, at the inverter 102 provided on the next stage of the transfer gate G1, the difference between the rise-time and the fall-time is small. Further, at the NAND gate 106, the difference between the rise-time and the fall-time is small. Therefore, the operation of the master FF in the falling of the input signal data, is more influenced by a delay caused by the insufficient current supply capacity of the P-channel transistor Tr5, as compared to the operation of the master FF in the rising of the input signal data. As a result, it is delayed that the signal is outputted from the node N3 which is an output terminal of the master FF.
In the concrete, as shown in the operation timing chart of FIG. 4, when the voltage of the input signal data rises, the input signal data passes through the node N3 at the time t52. On the other hand, when the voltage of the input signal data falls, the input signal data passes through the node N3 at the time t54. The input signal data is delayed when the voltage of the input signal data falls. The operation time difference between the rise-time and the fall-time is caused.
The slave FF comprises a four-stage circuit (the transfer gate G3, the NAND gate 107 and the inverters 104 and 105) from the node N3 to an output terminal {overscore (OUT)}. Therefore, the pass time of the slave FF is too long. The whole tpd (Time for Propagation Delay) becomes long.
In order to solve the above-described problems, an object of the present invention is to improve the delay of the operation of the master flip-flop of the D-FF circuit in the falling of the input signal data, and to shorten the tpd in the slave flip-flop in order to operate the D-FF circuit at a high speed.
That is, in accordance with one aspect of the present invention, a D-FF circuit (for example, a D-FF circuit 3 shown in FIG. 1A) comprises:
a master flip-flop and a slave flip-flop which operate in accordance with a plurality of clock signals generated by a clock signal generating circuit (for example, a clock signal generating circuit 4 shown in FIG. 1B);
wherein the slave flip-flop comprises:
a clocked inverter (for example, a clocked inverter 120 shown in FIG. 1A) which is disposed on a first stage of the slave flip-flop and which operates in accordance with at least one of the plurality of clock signals generated by the clock signal generating circuit, and
a two-stage inverter (for example, inverters 113 and 114 shown in FIG. 1A) which is connected in series with an output terminal of the clocked inverter.
According to one aspect of the present invention, the slave flip-flop can have a three-stage construction. The tpd can be improved. As a result, the operation speed of the D-FF circuit can be higher.
In accordance with another aspect of the present invention, a D-FF circuit (for example, a D-FF circuit 3 shown in FIG. 1A) comprises:
a master flip-flop and a slave flip-flop which operate in accordance with a plurality of clock signals generated by a clock signal generating circuit (for example, a clock signal generating circuit 4 shown in FIG. 1B);
wherein the master flip-flop comprises:
a transfer gate (for example, a transfer gate G1 shown in FIG. 1A) for transmitting an input signal in accordance with at least one of the plurality of clock signals generated by the clock signal generating circuit, and
an element (for example, a NOR gate 110 shown in FIG. 1A) for outputting the input signal by giving a predetermined pass time so as to eliminate a transmission time difference of the transfer gate between a rising of the input signal and a falling of the input signal.
According to another aspect of the present invention, the operation time difference of the master flip-flop between the rising of the input signal and the falling thereof can be improved. The operation speed of the D-FF circuit can be higher.
In accordance with another aspect of the present invention, a D-FF circuit (for example, a D-FF circuit 3 shown in FIG. 1A) comprises:
a master flip-flop and a slave flip-flop which operate in accordance with a plurality of clock signals generated by a clock signal generating circuit (for example, a clock signal generating circuit 4 shown in FIG. 1B);
wherein the slave flip-flop comprises:
a clocked inverter (for example, a clocked inverter 120 shown in FIG. 1A) which is disposed on a first stage of the slave flip-flop and which operates in accordance with at least one of the plurality of clock signals generated by the clock signal generating circuit, and
two-stage inverters (for example, inverters 113 and 114 shown in FIG. 1A) which is connected in series with an output terminal of the clocked inverter; and
the master flip-flop comprises:
a transfer gate (for example, a transfer gate G1 shown in FIG. 1A) for transmitting an input signal in accordance with at least one of the plurality of clock signals generated by the clock signal generating circuit, and
an element (for example, a NOR gate 110 shown in FIG. 1A) for outputting the input signal by giving a predetermined pass time so as to eliminate a transmission time difference of the transfer gate between a rising of the input signal and a falling of the input signal.
According to the present invention, the slave flip-flop can have a three-stage construction. The tpd can be improved. Further, the operation time difference of the master flip-flop between the rising of the input signal and the falling thereof can be improved. The operation speed of the D-FF circuit can be higher.
The element may be a NOR circuit element.
The signal is outputted slowly in the rising of the signal, and is outputted fast in the falling of the signal by using the NOR circuit element. Therefore, the operation delay of the master flip-flop in the falling of the input signal, can be improved.
The master flip-flop and the slave flip-flop may be made from CMOS.
Because the D-FF circuit is made from CMOS, the operation speed thereof can be higher.